This is an invention that generally relates to semiconductor memory devices . More specifically, this invention pertains to a dynamic random access memory called DRAM, and to a method of manufacturing it.
Various attempts have been made to increase the density of memory devices on the small area of a semiconductor memory chip. For example, there is a known fabrication technique in which, in order to minimize a memory cell area to increase the density of semiconductor memory devices, the storage capacitor is formed over the transistor serving as a switch. Two types of memory cells are known, one in which the bit line is formed over the storage capacitor which is thus called the "bit-line-over-storage-capacitor organization cell" (hereinafter referred to as the "BLOSC" organization cell) and the other in which the bit line is formed under the storage capacitor which is thus called the "bit-line-under-storage-capacitor organization cell" ( the BLUSC organization cell) .
An example of prior art semiconductor memory devices is described below.
FIG. 20 shows the cross section of a conventional semiconductor memory device employing the BLUSC organization cell, and FIG. 21 shows the corresponding layout. The body of this prior art semiconductor memory device is composed of a p-type semiconductor substrate 1, an ion diffused layer 2 made up of a drain 8 and a source 4 both formed locally in the p-type semiconductors substrate 1, an isolation region 5 that is used for electrical insulation from the neighboring ion diffused layer 2, a word line 6, a gate oxide 7, and a gate 8 that is part of the word line 6 lying over the gate oxide 7. The drain 3, the source 4, and the gate 8 together constitute a switching transistor 9. A first dielectric layer 10 is formed of BPSG (B,P-doped SiO.sub.2). A bit line contact 11 is formed on the drain 3. A bit line 12 is formed of n.sup.+ polysilicon and WSi.sub.2.7. The bit line 12 is electrically connected to the drain 3 through the bit line contact 11. A second dielectric layer 13 is formed of BPSG. A storage capacitor contact 18 is formed on the source 4. A storage capacitor electrode 20, of n.sup.+ polysilicon, is electrically connected to the source 4 via the storage capacitor contact 18. A capacitor insulation layer 21 is of a multilayered structure formed of layers of SiO.sub.2 and Si.sub.3 N.sub.4. A plate electrode 22 is formed of n.sup.+ polysilicon which, together with the storage capacitor electrode 20 and the capacitor insulation layer 21, constitutes a storage capacitor 23. A third dielectric layer 15 is formed of BPSG. A first upper-level wire 14 is of a multilayered structure formed of layers of Ti, TiN, and AlSiCu (Si, Cu-doped Al). A fourth dielectric layer 17 is formed of SiO.sub.2 formed by decomposing tetraethylorthosilicate (abbreviated TEOS), Si(OC.sub.2 H.sub.5).sub.4. A second upper-level wire 16 is of a multilayered structure formed of layers of Ti, TiN, and AlSiCu.
FIG. 22 is a schematic top section of a conventional semiconductor memory device with the BLOSC organization cell, and like elements are indicated by like reference numerals throughout the figures.
Due to the foregoing organization, the following drawbacks arise.
In the first place, since the peripheral circuit region does not have the storage capacitor 23, the substrate height of the upper-level wire greatly varies between the peripheral circuit region and the memory cell region. This presents a problem that the allowance of focus decreases during the patterning for transferring a pattern of the upper-level wire onto the memory cell region and the peripheral circuit region at the same time by means of a photolithographic process.
In the second place, following the step of forming the storage capacitor 23, the substrate of the first upper-level wire 14 is leveled with a high-temperature heat treatment. This prevents not only the use of a high dielectric layer formed of such a material of TaO.sub.x whose dielectric characteristic is degraded when treated at high temperatures but also the use of a strong dielectric layer formed of such a material as PZT(Pb (Zr.sub.x Ti.sub.1-x)O.sub.3), as the material for the capacitor insulation layer 21 of the storage capacitor 23.
In the last place, in the semiconductor memory device of the BLOSC organization of FIG. 22, the bit line contact 11, which connects the bit line 12 lying over the storage capacitor electrode 20 to the drain 3 of the switching transistor 9 lying under the storage capacitor electrode 20, and the storage capacitor electrode 20 coexist in the same layer. Thus, the area of the storage capacitor electrode 20 is reduced by the area occupied by the bit line contact 11. This leads to the decrease of the capacitance of the storage capacitor, compared to the BLUSC organization cell of FIG. 21. In the semiconductor memory device with the BLUSC organization cell, on the other hand, the bit line contact 11 for connection between the bit line 12 and the drain 3 must be provided under the bit line 12, and the storage capacitor contact 18 for connection between the storage capacitor electrode 20 and the source 4 must be provided beside the bit line 12. As a result, the drain 3 and the source 4 are asymmetrical with the word line 6. Due to this, the area of the ion diffused layer 2 excessively increases by the area of a portion 30 of FIG. 21, compared to the BLOSC organization cell where the drain 3 and the source 4 are symmetrical in relation to the word line 6. As a result, the area per unit cell disadvantageously increases as compared to the BLOSC organization cell thereby preventing the density of semiconductor memory devices from increasing.
Japanese Patent Application published under Pub. No. 2-137363 meanwhile discloses a technique for increasing the capacity of storage capacitors. In this prior art technique, two storage capacitors, with intervening a dielectric layer between them, are provided thereby attempting to increase the capacity without increasing the size of semiconductor memory devices. This, however, presents a problem that the provision of such two storage capacitors in the two layers results in the increase of thickness to upper-level wiring. This also allows for the allowance of focus to decrease during the photolithographic process.